djtechno
Unregistered
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Das Projekt ist aber noch im absoluten Anfangsstadium, Schaltplan wird dann auch noch gemacht, sobald der Code für alle 5 AVRs steht
Beitrag #11663
RE: Auffangstation der Nachteulen :-)
Ich programmiere für 5 AVR µC's grade den Mega Derben deterministischen Trash-Synth-Algorythmus in Assembler Big Grin
In jedem AVR werden die Eingänge gelesen, abhängig von der Bitkombination in ein anderes unterprogramm gewechselt, in dem von allen ports die pins eingelesen, ge-xort,added, shiftet und so weiter werdsen, rausgeschrieben, in allen möglichen Kombinationen auf die ausgänge rausgeschrieben und wieder ins hauptprogramm gewechselt. Wenn die individuellen codes für alel 5 µcs fertig sind, dann kommen an die eingänge des ersten lauter taster, die ausgänge des ersten an die eingänge des zweiten, dessen ausgänge an die eingänge des dritten, und paralel dazuwird über ein widerstandsnetzwerk von alles ausgängen aller µcs quasi ein x-bit-d/a-wandler gebaut!
ALDER, was auch imer da nachher für sounds rauskommen, das ding wird RICHTIG speziell 8)
Code: .NOLIST
.INCLUDE "8515def.inc"
.LIST
.DEF mp = R16
.EQU d_in_spiegel=PINC + $20
rjmp main
main: LDI mp,LOW(RAMEND) ;Initiate Stackpointer
ldi R20,255
OUT SPL,mp
LDI mp,HIGH(RAMEND)
OUT SPH,mp
ldi mp,0b11111111
out DDRB,mp
LDI mp,0x00 ; 8 Nullen in Universalregister
out ddra,mp
out ddrc,mp
OUT DDRD,mp ; an Datenrichtungsregister
LDI mp,0xFF ; 8 Einsen in Universalregister
out porta,mp
out portc,mp
OUT PORTD,mp ; und an Port D (das sind jetzt die Pull-Ups!)
LDI mp,0xFF ; 8 Einsen in Universalregister
OUT DDRB,mp ; und in Datenrichtungsregister
OUT PORTB,mp
loop:
ldi mp,0x00
out PORTB,mp
ldi mp,0xFF
out PORTB,mp
ldi R26,LOW(d_in_spiegel) ; unteres Byte Zeiger
ldi R27,HIGH(d_in_spiegel) ; oberes Byte Zeiger
ld mp,X
in mp,PINC ; Lese Schalter-Port
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs prog1a
rjmp t2
prog1a: rjmp prog1
t2: in mp,PINC ; Lese Schalter-Port
lsr mp
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs prog2a
rjmp t3
prog2a: rjmp prog2
t3: in mp,PINC ; Lese Schalter-Port
lsr mp,2
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs prog3A
rjmp t4
prog3a: rjmp prog3
t4: in mp,PINC ; Lese Schalter-Port
lsr mp,3
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs prog4a
rjmp t5
prog4a: rjmp prog4
t5: in mp,PINC ; Lese Schalter-Port
lsr mp,4
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs prog5a
rjmp t6
prog5a: rjmp prog5
t6: in mp,PINC ; Lese Schalter-Port
lsr mp,5
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs prog6a
rjmp t7
prog6a: rjmp prog6
t7: in mp,PINC ; Lese Schalter-Port
lsr mp,6
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs prog7a
rjmp t8
prog7a: rjmp prog7
t8: in mp,PINC ; Lese Schalter-Port
lsr mp,7
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs prog8a
rjmp t9
prog8a: rjmp prog8
t9:
in mp,PINA ; Lese Schalter-Port
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs nrog1a
rjmp t10
nrog1a: rjmp nrog1
t10: in mp,PINA ; Lese Schalter-Port
lsr mp
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs nrog2a
rjmp t11
nrog2a: rjmp nrog2
t11: in mp,PINA ; Lese Schalter-Port
lsr mp,2
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs nrog3a
rjmp t12
nrog3a: rjmp nrog3
t12: in mp,PINA ; Lese Schalter-Port
lsr mp,3
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs nrog4a
rjmp t13
nrog4a: rjmp nrog4
t13: in mp,PINA ; Lese Schalter-Port
lsr mp,4
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs nrog5a
rjmp t14
nrog5a: rjmp nrog5
t14: in mp,PINA ; Lese Schalter-Port
lsr mp,5
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs nrog6a
rjmp t15
nrog6a: rjmp nrog6
t15: in mp,PINA ; Lese Schalter-Port
lsr mp,6
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs nrog7a
rjmp t16
nrog7a: rjmp nrog7
t16: in mp,PINA ; Lese Schalter-Port
lsr mp,7
rol mp ; Schiebe siebtes Bit in das Carry-Flag
brcs nrog8a
rjmp t17
nrog8a: rjmp nrog8
t17: rjmp loop
prog6:
ldi mp,0
out DDRB,mp
out DDRD,mp
in mp,PINC
in R17,PINA
sub mp,R17
or R17,mp
ldi R21,0xff
out ddrb,R21
out ddrd,r21
out PORTB,mp
out PORTD,R17
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
ror mp
eor mp,R20
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
ldi R21,0b10110011
eor mp,R21
out PORTD,mp
ldi mp,0
out DDRB,mp
out DDRD,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINA
rol mp
ldi R21,45
and mp,R21
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
ldi R21,0b10101
add mp,R21
out PORTD,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
add mp,R17
ldi R21,12
or R17,R21
and R17,mp
rol mp
ldi R21,29
sub mp,R21
ror R17
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,R17
out PORTD,R17
rjmp loop
prog7:
ldi R18,0
innerloop1:
inc R18
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
add mp,R17
ldi R21,12
or R17,R21
and R17,R18
rol mp
sub mp,R18
ror R17
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,R17
out PORTD,R17
ldi R21,40
cp R18,R21
brcs innerloop1
rjmp loop
prog8:
ldi r21,0
out DDRB,r21
out DDRD,r21
ldi R18,44
innerloop2:
ldi R21,0b10100101
eor R18,R21
dec R18
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
add mp,R17
ldi R21,12
or R17,R21
and R17,R18
ror mp
eor mp,R20
sub mp,R18
rol R17
eor R17,R20
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,R17
out PORTD,R17
ldi R21,23
cp R18,R21
brcs innerloop2
rjmp loop
nrog1:
ldi r21,0
out DDRB,r21
out DDRD,r21
in R18,PINC
innerloop3:
ldi R21,0b10110101
eor R18,R21
in R21,PINA
add R18,R21
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
add mp,R17
ldi R21,27
and R17,R21
or R17,R18
rol mp
eor mp,R20
sub mp,R18
ror R17
eor R17,R20
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,R17
out PORTD,R17
ldi R21,47
cp R18,R21
brcs innerloop3
rjmp loop
nrog2:
ldi r21,0
out DDRB,r21
out DDRD,r21
in R18,PINA
innerloop4:
ldi R21,0b10110101
and R18,R21
in R21,PINA
eor R18,R21
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
add mp,R17
ldi R21,59
and R17,R21
eor R17,R18
eor R18,R20
rol mp
eor mp,R20
sub mp,R18
ror R17
eor R17,R20
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,R17
out PORTD,R17
ldi R21,31
cp R18,R21
brcs innerloop4
rjmp loop
nrog3:
ldi r21,0
out DDRB,r21
out DDRD,r21
in R19,PINC
in R18,PINA
innerloop5:
in R21,PINC
and R18,R21
in R21,PINA
eor R18,R21
in R21,PINC
eor R19,R21
in R21,PINA
or R19,R21
add R18,R19
in mp,PINC
in R17,PINA
add mp,R17
and R17,R19
eor R17,R18
eor R18,R20
rol mp
eor mp,R20
sub mp,R18
or mp,R19
ror R17
eor R17,R20
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,R17
out PORTD,R17
ldi R21,87
cp R18,R21
brcs innerloop5
rjmp loop
nrog4:
ldi r21,0
out DDRB,r21
out DDRD,r21
in R19,PINC
in R18,PINA
innerloop6:
in R21,PINC
and R18,R21
in R21,PINA
or R18,R21
in R21,PINC
and R19,R21
in R21,PINA
or R19,R21
add R18,R19
lsr R19,R18
in mp,PINC
in R17,PINA
add mp,R17
lsl R17,R19
eor R17,R18
eor R19,R20
rol mp
eor mp,R20
sub mp,R19
add mp,R18
rol R17
eor R17,R20
rol R18
ror R19
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,R17
out PORTD,R17
LDI R21,14
cp R18,R21
brcs innerloop6
rjmp loop
nrog5:
ldi r21,0
out DDRB,r21
out DDRD,r21
in R19,PINA
in R18,PINC
innerloop7:
in R21,PINC
and R18,R21
in R21,PINA
eor R18,R21
in R21,PINC
and R19,R21
in R21,PINA
eor R19,R21
sub R18,R19
lsl R19,R18
in mp,PINA
in R17,PINC
add mp,R17
lsl R17,R19
eor R17,R18
eor R19,R20
rol mp
eor mp,R20
sub mp,R19
add mp,R18
rol R17
ldi R21,44
eor R17,R21
rol R18
sub R18,R17
add R19,mp
rol R19
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTD,R17
out PORTB,R17
ldi R21,99
cp R18,R21
brcs innerloop7
rjmp loop
nrog6:
ldi r21,0
out DDRB,r21
out DDRD,r21
in R19,PINA
in R18,PINC
innerloop8:
in R21,PINA
and R18,R21
in R21,PINA
or R18,R21
in R21,PINC
and R19,R21
in R21,PINA
add R19,R21
and R18,R19
lsr R19,R18
in mp,PINA
in R17,PINC
eor mp,R17
lsl R17,R19
sub R17,R18
ror mp
add mp,R19
and mp,R18
rol R17
LDI r21,44
eor R17,r21
rol R18
sub R18,R17
add R19,mp
rol R19
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTD,R17
out PORTB,R17
ldi r21,77
cp R18,r21
brcs innerloop8
rjmp loop
nrog7:
ldi r21,0
out DDRB,r21
out DDRD,r21
in R19,PINA
in R18,PINC
innerloop9:
ldi r21,66
and R18,r21
in r21,PINC
or R18,r21
ldi r21,47
and R19,r21
in r21,PINA
add R19,r21
add R18,R19
lsl R19,R18
rol R19
in mp,PINA
in R17,PINC
or mp,R17
lsr R17,R19
ldi r21,89
sub R17,r21
rol mp
add mp,R19
and mp,R18
rol R17
ldi r21,97
eor R17,r21
rol R18
sub R18,R17
add R19,mp
rol R19
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTD,R17
out PORTB,R17
ldi r21,66
cp R18,r21
brcs innerloop9
rjmp loop
nrog8:
ldi r21,0
out DDRB,r21
out DDRD,r21
in R19,PINA
in R18,PINC
innerloop10:
ldi r21,34
and R18,r21
in R21,PINC
or R18,r21
ldi r21,91
add R19,r21
in r21,PINA
add R19,r21
sub R18,R19
lsr R19,R18
rol R19
in mp,PINA
in R17,PINC
eor mp,R17
lsr R18,R19
ldi r21,74
add R17,r21
ror mp
add mp,R16
sub mp,R19
ror R16
ldi r21,65
eor R17,r21
rol R19
ldi r21,23
sub R16,r21
and R19,mp
ror R19
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTD,R17
out PORTB,mp
ldi r21,47
cp R18,r21
brcs innerloop10
rjmp loop
prog2:
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
rol mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
ldi r21,0b10101111
eor mp,r21
out PORTD,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINA
ror mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
ldi r21,0b1010
add mp,r21
out PORTD,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
lsr mp,2
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
rol mp
rol mp
out PORTD,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINA
lsl mp,2
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
ldi r21,44
sub mp, r21
out PORTD,mp
rjmp loop
;
prog3:
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
add mp,R17
eor R17,mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
out PORTD,R17
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
sub mp,R17
lsr R17,mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
out PORTD,R17
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
sub mp,R17
lsr R17,mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,R17
out PORTD,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
add mp,R17
eor R17,mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,R17
out PORTD,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
sub mp,R17
lsr R17,mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,R17
out PORTD,R17
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
add mp,R17
eor R17,mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,R17
out PORTD,R17
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
sub mp,R17
lsr R17,mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
out PORTD,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
add mp,R17
eor R17,mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
out PORTD,mp
rjmp loop
prog4:
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
add mp,R17
eor R17,mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
out PORTD,R17
lsl mp,R17
eor R17,mp
out PORTD,mp
out PORTB,R17
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
add mp,R17
rol mp
eor R17,mp
ror R17
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
out PORTD,R17
lsl mp,R17
ror mp
eor R17,mp
rol R17
out PORTD,mp
out PORTB,R17
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
sub mp,R17
rol mp
and R17,mp
ror R17
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
out PORTD,R17
lsr mp,R17
rol mp
or R17,mp
rol R17
out PORTD,mp
out PORTB,R17
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
sub mp,R17
ror mp
and R17,mp
eor R17,R20
ror R17
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
out PORTD,R17
lsr mp,R17
eor mp,R20
lsr R17,mp
eor R17,R20
out PORTD,mp
out PORTB,R17
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
sub mp,R17
eor mp,R20
and R17,mp
eor R17,R20
ldi r21,3
sub mp,r21
ror R17
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
out PORTD,R17
lsr mp,R17
eor mp,R20
ldi r21,88
add R17,r21
lsl R17,mp
eor R17,R20
out PORTD,mp
out PORTB,R17
rjmp loop
prog5:
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
in R17,PINA
sub mp,R17
eor R17,R20
and R17,mp
eor mp,R20
ldi r21,15
sub mp,r21
rol R17
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,R17
out PORTD,R17
lsr mp,R17
eor R17,R20
ldi r21,43
or R17,r21
lsl R17,mp
eor R17,R20
out PORTD,mp
out PORTB,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINA
in R17,PINC
sub mp,R17
rol R17
and R17,mp
ror mp
eor mp,R20
ldi r21,54
sub mp,r21
ror R17
eor mp,R20
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
out PORTD,mp
lsr mp,R17
ldi r21,0b10110001
or R17,r21
inc R17
ldi r21,43
eor R17,r21
lsl R17,mp
eor R17,R20
out PORTD,R17
out PORTB,R17
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINA
in R17,PINC
sub mp,R17
rol R17
and R17,mp
eor R17,R20
ror mp
ldi r21,53
sub mp,r21
rol R17
eor mp,R20
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
out PORTD,R17
lsr mp,R17
ldi r21,0b10001111
or R17,r21
ldi r21,22
add R17,r21
ldi r21,78
eor R17,r21
lsl R17,mp
out PORTD,mp
out PORTB,R17
rjmp loop
prog1:
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
rol mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINA
ldi r21,0b10100101
eor mp,r21
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTD,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
ror mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTD,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINA
ldi r21,0b01011010
eor mp,r21
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
rol mp
inc mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINA
ldi r21,0b10100101
eor mp,r21
dec mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTD,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINC
ror mp
inc mp
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTD,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINA
ldi r21,0b01011010
eor mp,r21
lsl mp,2
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
ldi r21,0
out DDRB,r21
out DDRD,r21
in mp,PINA
ldi r21,0b01011010
eor mp,r21
lsr mp,2
ldi r21,0xff
out DDRB,r21
out DDRD,r21
out PORTB,mp
rjmp loop
Bin mal heute Abend egspannt, obs läuft, dann muß ich mal kucken, daß ich erstmal sowas wie einen Simulator bekomme, weil mit dem usb flasher kann man glaube ich den AVR nicht live debuggen 
Bevor ich die ganze Schaltung zusammenbaue, will ich erstmal die einzelnen Programme durchprüfen.
edit: code gefixt, tut nun
edit2: nochmal gebugfixt, hoffe,es stimmt nun so.
edit3: Nochmal geupdatet, nun stimmt es definitiv, leider habe ich genau den atmel nicht, für den der code ist aber werde den noch kaufen.
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